1. Field of the Invention
The present invention relates generally to flash memory and in particular the present invention relates to using microcrystalline polysilicon film as a floating gate to improving the performance of memory cell.
2. Description of the Prior Art
A typical flash memory comprises a memory array, which includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The presence or absence of the charge in the floating gate determines the data in a cell.
FIG. 1 is a cross-sectional view of a typical memory cell 5, such as a used in a flash memory. Memory cell 5 comprises a region of a source 60 and a region of a drain 70. Source 60 and drain 70 are separated by a predetermined space of a channel 80 region. Memory cell 5 further includes a floating gate 30 formed by a first polysilicon layer, and a control gate 50 formed by a second polysilicon layer. Floating gate 30 is isolated from control gate 50 by an interpoly dielectric layer 40 and from channel region 80 by a thin oxide layer (tunnel oxide layer) 20 approximately 100 angstroms thick.
FIG. 2 shows a magnified cross-section of a floating gate by using a polysilicon layer 84 formed on substrate 82 such as a tunnel oxide. Polysilicon layer 84 is formed by depositing silicon onto the surface of substrate 82 in a low pressure chemical vapor deposition (LPCVD) chamber at a temperature of approximately 600° C. by using silane (SiH4) chemistry. The grain size of polysilicon is about 1000 angstrom and about 2000 angstrom. The surface roughness of polysilicon layer 84 is a result of the large-grained columnar crystal structures within the film. This pronounced surface roughness makes it difficult to obtain good patterning profiles due to the significant variation in inter granular thickness of photoresist formed on the surface of the polysilicon layer 84, and the non-uniformity in reflectivity which occurs during the photolithographic patterning process. The non-uniformity in reflectivity of photoresist layer is forms bad etching profiles and makes it easy to obtain the poly stringer issue.
FIG. 3 shows a magnified cross-section of another floating gate by using a polysilicon layer 88 formed on substrate 86 such as a tunnel oxide. Polysilicon layer 88 is formed by a process in which silicon is deposited on the surface of a substrate in a LPCVD chamber at a temperature of approximately 550° C. By depositing silicon at this lower temperature, amorphous silicon is created because crystal grains cannot develop at this low temperature. This amorphous silicon is subsequently recrystallized by exposing the material to a temperature in excess of 600° C. The result is the polycrystalline structure shown in FIG. 3, wherein large crystal grains are formed. While the polysilicon layer 88 of FIG. 3 overcomes the problems associated with surface roughness described above of FIG. 2. The large grain size of polysilicon layer 88 reduces the grain boundary density of the film. In addition, because the polysilicon layer 88 is deposited at a low temperature, the deposition rate is similarly low, resulting in slow throughput times.
The storage or erase of the flash memory cell as shown in FIG. 1 is programmed by Fowler-Nordheim tunneling of electrons through a thin tunnel oxide layer between the floating gate and the channel. The thin tunneling oxide generally is about 100 angstroms. In the programming mode for flash memory, hot carriers tunnel from the channel to the floating gate and are stored in the floating gate. The control gate, the select gate and the drain of the flash memory cell are positively biased while the source is grounded. In erase mode, usually programmed, the drain is biased at high voltage to finish the erase process.
An over erased memory cell has a faster erase speed, which means a higher electron current through the tunneling oxide. When using large grain polysilicon floating gate to cause wider threshold voltage (Vt) distribution. If over erased blocks exist, threshold voltage distribution after erase has tail components and larger variance value. In other words, the wider erase threshold voltage distribution corresponds to large polysilicon grains.
In conventional to flash memory process, by using large grain polysilicon film as a floating gate. There are many drawbacks such as over erasing, wider threshold voltage distribution, tail bit issue, tunnel oxide quality down, higher polysilicon resistance and bed etching profile due to poly stringer issue.